The present invention relates to a circuit used to regulate the read-back voltage applied to address lines of a memory circuit during a read-back operation. More specifically, the present invention relates to a circuit that provides a read-back voltage as an adjustable percentage of a core supply voltage, with the ability to select the specific percentage depending on the actual level of the core supply voltage.
Programmable logic devices, such as field programmable gate arrays (FPGAs), include configuration memory cells that are loaded with configuration data values. These configuration data values control the configuration of the programmable logic device. FPGAs often include a read-back mechanism that enables the previously written configuration data values to be read from the configuration memory cells.
FIG. 1 shows a conventional array of configuration memory cells (i.e., a configuration memory) such as used by Xilinx, Inc., assignee of the present invention. The configuration memory of FIG. 1 is a 16-bit by 16-bit array, which includes 256 configuration memory cells. In general, each of the configuration memory cells is identified by a reference character MX,Y, where X and Y correspond with the row and column of the configuration memory cell. A typical array of configuration memory cells in a commercial device has on the order of 20,000 to one million memory cells. Thus the array of FIG. 1 is much smaller than is typically used in a commercial embodiment, but nevertheless shows the structure of prior art configuration memories. To load the configuration memory, a bit stream of configuration data values (DATA) is shifted into data control circuit DC, under control of a clocking mechanism, until a frame of data (16 bits wide in this example) has been shifted into bit positions C0 through C15 of data control circuit DC. This frame of data is then routed from bit positions C0-C15 to data lines D0-D15, respectively. Note that only data lines D0 and D15 are labeled for purposes of clarity.
Address control circuit AC, which includes address drivers 0-15, drives a write enable signal onto one of the address lines A0-A15, thereby enabling the configuration data values on lines D0-D15 to be written to a column of the configuration memory cells. Note that only address lines A0 and A15 are labeled for purposes of clarity.
Hsieh in U.S. Pat. No. 4,750,155 describes a five transistor memory cell that can be reliably read and written by applying a lower read-back voltage to a memory cell access transistor than is applied to the memory cell access transistor to write a new value. The Hsieh patent is incorporated herein by reference.
FIG. 2 is a circuit of a conventional six-transistor configuration memory cell M0,0 that includes an n-channel access transistor T1, an n-channel reset transistor T2 and two CMOS inverters I1 and I2. As is well known in the CMOS design art, each of the two inverters I1 and I2 comprise one PMOS transistor and one NMOS transistor connected in series between the VDD supply voltage and ground. Inverters I1 and I2 are cross-coupled, thereby forming a latch. This latch is connected to data line D0 by access transistor T1, which is controlled by a control voltage on address line A0. One or more lines Q and/or Q# extends from configuration memory cell M0,0 to the FPGA logic structure (not shown) to control the configuration of this structure.
Configuration memory cell M0,0 is initially reset by turning on the n-channel reset transistor T2. This reset mechanism enables the transistors in inverters I1 and I2 to be made relatively small (because configuration memory cell M0,0 does not have to be reset via data line D0) While it is desirable to have relatively small transistors to reduce layout area, these small transistors undesirably result in relatively weak inverters I1 and I2. Thus, the configuration memory value stored by inverters I1 and I2 is more susceptible to being disturbed during a read back operation where the charge on a large data line can flip the value stored by the small memory cell.
To write a configuration data value to the first column of configuration memory cells M0,0-M15,0, address driver 0 is controlled to drive a write enable voltage equal to the VDD supply voltage to address line A0. This relatively high write voltage assures that the access transistors (e.g., access transistor T1) are completely turned on during the write operation, such that the configuration data values are properly written to the configuration memory cells.
The configuration data values stored in configuration memory cells M0,0-M15-15 can subsequently be read back to data control circuit DC on a column-by-column basis. For example, to read the configuration data values stored in the first column of configuration memory cells M0,0-M15,0, address control circuit AC causes address driver 0 to apply a read-back voltage to address line A0. This read-back voltage is typically selected to be equal to the VDD supply voltage minus the threshold voltage (VT) of access transistor T1. Under these conditions, the configuration data values stored in configuration memory cells M0,0 to M15,0 are read back to the data control circuit DC on data lines D0-D15. The read-back voltage is low enough to ensure that the read-back operation does not disturb the configuration data values stored in the configuration memory cells M0,0-M15,0. Note that the read-back voltage is referenced to the VDD supply voltage because the associated circuitry in data control circuit DC operates in response to the VDD supply voltage.
During normal operation, the VDD supply voltage can typically vary +/xe2x88x9210 percent with respect to a nominal supply voltage value. Thus, a VDD supply voltage having a nominal value of 1.2 Volts can vary from 1.08 to 1.32 Volts. For relatively low VDD supply voltages, the read-back voltage (VDDxe2x88x92VT) might be too low to reliably read the configuration memory cell. For example, a VDD supply voltage of 1.08 Volts would produce a read-back voltage of about 0.710 Volts, assuming a threshold voltage of 0.370 Volts. This read-back voltage may be inadequate to reliably read the configuration data values stored in the configuration memory cells.
It would therefore be desirable to have a method and apparatus for generating acceptable read-back voltages for a memory circuit, such as a configuration memory array of a programmable logic device, for all possible values of the VDD supply voltage.
Accordingly, the present invention provides a read-back voltage generation circuit that provides a read-back voltage as an adjustable percentage of a supply voltage. The read-back voltage generation circuit has the ability to select the specific percentage depending on the actual level of the supply voltage. For example, if the supply voltage has a relatively high value, then the read-back voltage will be a relatively low percentage of the supply voltage. Conversely, if the supply voltage has a relatively low value, then the read-back voltage will be a relatively high percentage of the supply voltage. As a result, the read-back voltage will always be high enough to reliably read the configuration data values from the configuration memory cells within a given time margin, but not so high as to overwrite these configuration data values. The read-back voltage generation circuit is especially advantageous for use in a chip having a low core supply voltage, wherein a threshold voltage drop (VT) represents a large percentage of the core supply voltage.
In one embodiment, the read-back voltage generation circuit buffers the read-back voltage through a low output impedance buffer that is capable of supplying the proper voltage for the address lines on the chip. The read-back voltage generation circuit is designed to use minimal DC current, but is still able to charge the address lines quickly and efficiently to a value that properly controls the read-back function.
In accordance with one embodiment, the read-back voltage generation circuit includes a comparator configured to receive the supply voltage and a reference voltage. The voltage generation circuit activates a select signal if the supply voltage has a predetermined relationship with respect to the reference voltage, and de-activates the select signal if the supply voltage does not exhibit the predetermined relationship with respect to the reference voltage. For example, the comparator can activate the select signal if the supply voltage is less than the reference voltage, and de-activate the select signal if the supply voltage is greater than the reference voltage.
An adjustable voltage divider circuit is coupled to receive the supply voltage and the select signal. The adjustable voltage divider circuit is configured in response to the select signal to provide an output voltage that is a first percentage of the supply voltage if the select signal is activated, and provide an output voltage that is a second percentage of the supply voltage if the select signal is de-activated. For example, the adjustable voltage divider circuit can be configured to provide an output voltage that is 95-100 percent of the supply voltage if the select signal is activated, and provide an output voltage that is less than 95 percent of the supply voltage if the select signal is de-activated. A low impedance, current limited output driver drives the output voltage as the read-back voltage.
In one embodiment, the reference voltage is derived from a bandgap voltage generator, thereby providing a relatively constant reference voltage.
One variation of the present invention uses multiple comparators to compare the supply voltage to a plurality of reference voltages. Such a variation enables finer control over the read-back voltage level.
The present invention will be more fully understood in view of the following description and drawings.